| 摘要 |
<p>PROBLEM TO BE SOLVED: To make the testing process omissible by frequency-dividing clock signal, passing it through a critical path and inputting it to a signal processing means and connecting the output and the clock signal to a measurement means by way of another signal processing means. SOLUTION: The logical product of an output signal 2A of clock signal frequency divider 21 and an output signal 2B having passed a critical pathγconstituted of a plurality of logic gates 22 is calculated by an AND circuit 26 of the first signal processing means. The output signal 2C and a system clock signal 2E from an external system clock input part 24 are input in the NAND circuit 27 of the second signal processing means to perform an operation. The number of pulses obtained by the operation is counted by a binary counter 23 of a measurement means. That is, the difference between the signal 2A and the signal 2B is obtained, and the operating speed is judged by a possible operating speed judgment circuit. By this constitution, an operating speed selection test can be done inside the chip by a self test circuit and test items may be reduced.</p> |
