| 摘要 |
The device includes, for each column of the memory, a precharge circuit and an amplifier. The amplifier includes two inverters each formed by two complementary transistors and controlled by two successive signals, read and rewrite. The amplifier includes a decoupling structure connected between the two P-channel transistors and the two N-channel transistors of the inverters and is formed by two pairs of complementary decoupling transistors connected in parallel. The decoupling structure is able on command to take at least a first state in which all the decoupling transistors are on, and a second state in which the two decoupling transistors having a channel with the same type of conductivity are on, while the other two decoupling transistors are off.
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