发明名称 |
SERIAL DATA TRANSMITTING SYSTEM |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide the serial data transmitting system of a low bit error rate, where a program controlling a unit operation and a program controlling communication coexist in a microcomputer whose number of processing bits is small, the execution efficiency of a main processing by an interruption processing is low and high speed data transmission is possible. SOLUTION: CPU 21 being the signal processing part of a reception side executes an outer interruption processing by input to an outer interruption port INT and starts a reception serial clock. Then, CPU 21 samples data inputted to a serial data input port SI in synchronizing with the rise of the reception serial clock and sequentially stores it in a serial register 219. CPU 21 collectively transfers data of the serial register 219 to a majority judgment means by a serial interruption means when data on the number of bits of the serial register 219 is inputted to the serial register 219.</p> |
申请公布号 |
JPH11219338(A) |
申请公布日期 |
1999.08.10 |
申请号 |
JP19980019904 |
申请日期 |
1998.01.30 |
申请人 |
MATSUSHITA ELECTRIC WORKS LTD |
发明人 |
FURUYA TOMOHIDE;SAKAMOTO HIDEO;TANIGAWA YOSHIHIRO |
分类号 |
G06F13/38;H04L7/00;H04L25/08;H04L25/40;(IPC1-7):G06F13/38 |
主分类号 |
G06F13/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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