| 摘要 |
A cache memory control architecture within a RAID storage subsystem which simplifies the migration and porting of existing ("legacy") control methods and structures to newer high performance cache memory designs. A centralized high speed cache memory is controlled by a main memory controller circuit. One or more bus bridge circuits adapt the signals from the bus architecture used by the legacy systems to the high speed cache memory. The bus bridge circuits each adapt, for example, a PCI bus used for a particular cache access purpose to the signal standards of an intermediate shared memory bus. The main memory controller circuit adapts the signals applied to the intermediate shared memory bus to the high speed cache memory bus. The hierarchical bus architecture permits older "legacy" control methods and structures to be easily adapted to newer cache memory architectures. In addition, the centralized high speed cache memory and associated legacy system busses serve to distribute the load of cache memory access over simultaneously operable busses. The cache memory architecture of the present invention therefore permits rapid porting and re-usability of older "legacy" control methods and structures while permitting the overall cache memory performance to be scaled up to higher bandwidth demands of modern RAID subsystems.
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