发明名称 CLOCK INPUT CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To reduce power consumption in an object by controlling an operation reference clock to be supplied to the object. SOLUTION: Two OR gates 31 and 32 supplied with the operation reference clock CK0 and call signals SC respectively supply the clock CK0 to the logic circuits 41 and 42 of the object when the call signal SC is 'L' and stop the supply when the call signal SC is 'H'. By the supply stoppage of the clock CK0 , the power consumption of the logic circuits 41 and 42 is reduced. In the meantime, the clock CK0 and the clock CK1 are supplied to the OR gate 33. For the clock pulse of the clock CK1 , a cycle is longer and a pulse width is longer than the clock CK0 . The OR gate 33 supplies the clock CK0 to the logic circuit 43 while the clock pulse of the clock CK1 is supplied. Thus, since the logic circuit 43 is intermittently operated, the power consumption is little.</p>
申请公布号 JPH11219226(A) 申请公布日期 1999.08.10
申请号 JP19980020070 申请日期 1998.01.30
申请人 OKI MICRO DESIGN MIYAZAKI CO LTD;OKI ELECTRIC IND CO LTD 发明人 YAMADA TOSHIMI;TAKASU RYUICHI
分类号 G06F1/32;G06F1/04;(IPC1-7):G06F1/04 主分类号 G06F1/32
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