Unit cell layout and transfer gate design for high density DRAMs having a trench capacitor with signal electrode composed of three differently doped polysilicon layers

摘要

A DRAM unit cell is disclosed which comprises a trench capacitor having a signal electrode, a bit line, a planar active word line overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the trench capacitor and the bit line and a gate electrode formed by the active word line.