| 摘要 |
A multiplier in a data processing system has a modified compressor structure which is configured to alleviate both a tendency of the multiplier to be wire bound and to optimize a circuit area required to implement the multiplier. In the modified compressor structure, all inputs to the compressor are not of the same weight, all outputs of the compressor are not of the same weight, and carry values generated during the compression process are no longer all shifted in a same direction. Instead, in the compressor, a mixture of sum values and carry values generated during a compression process are reduced within the compressor. By modifying the compressor so that it is no longer limited to receiving only inputs having a same weight, there is a reduced input/output signal requirement and, therefore, the compressor has less global interconnect requirements. Additionally, the layout of the compressor reduces an amount of "stagger" of multiplier because the weight of the values provided by the input Booth multiplexers to the compressor are not required to be the same.
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