发明名称 CLOCK SYNCHRONIZING CIRCUIT
摘要 A clock synchronizing circuit comprises a voltage controlled oscillator (VCO) for producing an output signal whose oscillation frequency changes in response to control signals. A phase comparator compares a phase of an input signal and a phase of the output signal to thereby generate a phase difference signal. A filter filters the phase difference signal to thereby output a filtered phase difference signal. A frequency synchronizing circuit responsive to the filtered phase difference signal generates a first compensation signal for controlling a frequency of the output signal. A phase synchronizing circuit responsive to the filtered phase difference signal generates a second compensation signal for controlling a phase of the output signal. A signal supplying circuit feeds the first and second compensation signals as said control signals.
申请公布号 CA2114268(C) 申请公布日期 1999.08.10
申请号 CA19942114268 申请日期 1994.01.26
申请人 发明人 NEZU, TOSHIYA
分类号 H03L7/113;H03L1/02;H03L7/093;H03L7/14;H04L7/00;(IPC1-7):H04L7/00 主分类号 H03L7/113
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