| 摘要 |
The present invention relates to a memory device including a sense amplifier for driving bit line pair and write amplifier for driving data bus line connecting to the bit line pair. According to the present invention, when the column gates are opened and the sense amplifiers are connected to the data bus amplifiers via the data bus pair, one sense amplifier circuit portion of each sense amplifier is deactivated and the conflicts which arise from the operation of the write amplifiers in the data bus amplifiers and of the sense amplifiers can be avoided, and the writing operation can be performed at a high speed. In addition, the control of the sense amplifiers need not be changed either for the reading process or for the writing process, and the writing speed can be increased without the reading being affected.
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