| 摘要 |
A programmable direction control scheme for an efficiently wired array of like integrated circuit chips which is capable of producing a rightward or leftward sequence of designated interaction is described. The member chips are incorporated into a system by connecting their existing addressing, data, and clock pads onto a mutual bus. The chips are additionally chained together by their qualification pads so that they may be individually designated for interaction with the system, by way of sequential token passing. A direction control bit within a programmable configuration register is included on each member chip in lieu of a dedicated input. The configuration register is given free access irrespective of the designation status of its incorporating chip, and thus the direction control bits of all of the member chips of the array may be expediently programmed even when the elsewise process of sequencing through the chips would be paradoxically self obstructed by an initial directional chaos condition. Also described is an additionally facilitated performance mode of operation which allows the above mentioned addressing pads to be transformed into additional data pads so that higher data throughput may be realized without adding pads. Both operational modes mutually share the programmable direction control. Also, the performance mode exercises automatic token passing, and an accessory mode provides for externally commanded token passing. Additionally described is an example usage of such chips within a print-bar application which has two arrays of chips, of which one row is upside down relative to the other.
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