发明名称 Multiplier with selectable booth encoders for performing 3D graphics interpolations with two multiplies in a single pass through the multiplier
摘要 A multiplier array is modified to perform interpolations. The interpolations use a normalized first operand A between 0 and 1. The interpolation is the function B * A+C * (1-A). Standard multipliers accept two operands as inputs, but interpolations require 3 operands (A, B, C). The AND gates in Booth encoders in a standard multiplier array are replaced by multiplexers. Each multiplexer selects a bit from one of the two operands (B or C) based on a bit of the first operand A. The interpolate operation multiplies the first operand A by the second operand B while simultaneously multiplying the bit-wise inverse of the first operand A' by the third operand C. Since one multiply is with the first operand A while the second multiply is with the inverse A' of the first operand, one of the multiplies always generates zero while the other multiply generates either a one or a zero for each bit of the first operand. The multiply producing zero is deleted by not being selected by the multiplexer; instead the multiplexer selects the other multiply as an intermediate product term. Thus the intermediate product terms for the half of the inputs which generate a zero product term are never generated. A correction term is generated and added in to account for the difference between the bit-wise inverse of A and the two's complement of A. The multiplexers can be enlarged to allow either standard 2-operand multiplies or 3-operand interpolations in the same multiplier array. The interpolator-multiplier is especially useful for 3D graphics applications.
申请公布号 US5935198(A) 申请公布日期 1999.08.10
申请号 US19960755545 申请日期 1996.11.22
申请人 S3 INCORPORATED 发明人 BLOMGREN, JAMES S.
分类号 G06T15/00;G06F7/483;G06F7/53;G06F7/533;G06F7/544;G06F17/17;G06T3/40;(IPC1-7):G06F7/38;G06F7/52 主分类号 G06T15/00
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