System for a multi-processor system wherein each processor transfers a data block from cache if a cache hit and from main memory only if cache miss

摘要

Data transmission control apparatus which controls data transmission between processing systems via a transmission line, each processing system including a memory system consisting of a main memory and a cache memory. The apparatus addresses data in the main memory by a memory address and gives an instruction to transmit the addressed data; determines whether or not the addressed data is in the cache memory; provides a match signal when the data is in the cache memory; reads the addressed data from the cache memory when instructed by the instruction and when a ready signal and the match signal are provided, and, otherwise reads the addressed data from the main memory; writes the data read into a port; transmits the data written in the port to the another processing system connected to the transmission line; and provides the ready signal when the port is ready to receive additional data.