Digital phase-locked loop for clock recovery

摘要

The invention relates to a phase-locked loop delivering a recovered clock signal from a reference clock signal Fref in which some transitions are missing. The loop includes a first divide-by-M frequency divider receiving the clock Fref and delivering a signal of frequency Fref/M; a phase comparator providing a phase error signal from the signal of frequency Fref/M, and the output signal from a second divide-by-M frequency divider; a divide-by-K frequency divider providing a signal of frequency Fk from a local oscillator signal of frequency FoL receiving the phase error signal as a control signal; an adder-counter of the division ratio p/q receiving the local oscillator signal of frequency FoL and delivering a signal of frequency Fo equal to FoL*p/q; a mixer delivering a signal of frequency Fn equal to Fo-Fk on the basis of signal of frequency Fk and the signal of frequency Fo; and a divide-by-N frequency divider synchronized by FoL, receiving the signal of frequency Fn, and delivering a recovered clock to the second divide-by-M frequency divider.