REED-SOLOMON DECODING DEVICE MADE INTO SERIES

摘要

PROBLEM TO BE SOLVED: To realize respective calculation parts with one cell, to reduce the overall area of a decoding device and to reduce power consumption by executing the decoding operation of code signals inputted by a bit clock in series. SOLUTION: A code data string inputted by a byte clock in a byte unit is divided into odd-numbered data and even-numbered data by an inverse multiplier 31 and they are inputted to respective adders 32a and 32b for calculating syndrome coefficient values for them. First multipliers 34a and 34b multiply a fixed constantα, supplied from a memory by a fixed constant 3a which is previously outputted in a bit clock period. One bit registers 35a and 35b temporarily store the fixed constant applied from the first multipliers 34a and 34b and output it to the second multipliers 33a and 33b. Eight bit shift registers 37a and 37b receive the input of the calculation results of the adders 32a and 32b and shift it by eight bits and output it.