发明名称 |
QUADRATURE FREQUENCY DIVISION MULTIPLEXING SIGNAL TRANSMITTER-RECEIVER |
摘要 |
<p>PROBLEM TO BE SOLVED: To make an accurate synchronizing signal easily obtainable on a receiving side. SOLUTION: A transmitter has an IFFT pilot signal generating circuit 3 which generates multilevel QAM signals, a guard interval setting circuit 4, and a clock signal generating circuit 10 which drives the circuits 3 and 4 and generates a pilot signal which has a high-order frequency and the phase of which is maintained constantly in a plurality of symbol sections. The pilot signal is set in such a way that the signal can exist an integeral multiple of wavelength or by a multiple of an odd number of a half wavelength and the signal can be sent out continuously over a plurality of symbol section including the above-mentioned symbol sections. A receiver generates a clock signal by demodulating the pilot signal.</p> |
申请公布号 |
JPH11215196(A) |
申请公布日期 |
1999.08.06 |
申请号 |
JP19980314404 |
申请日期 |
1998.11.05 |
申请人 |
VICTOR CO OF JAPAN LTD |
发明人 |
TAKAHASHI NOBUAKI;TAKAHASHI SUSUMU;SUGIYAMA KENJI |
分类号 |
H04L27/00;H04J11/00;H04L7/00;(IPC1-7):H04L27/00 |
主分类号 |
H04L27/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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