| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent complexity of a circuit constitution and a layout and facilitate control on write prior to deletion. SOLUTION: A binary counter 22 is set at a most significant point of an address counter 19 sequentially generating addresses of a memory cell array 11. Upon completion of the write prior to deletion to the memory cell array, the binary counter 22 forcibly selects a spare row 12, thus enabling the write prior to erasing. In the write prior to deletion, whether or not verification is to be executed is judged from a state of a coincidence signal RDHIT output from a failing address memory part 21.</p> |
