LSI SCAN TEST DESIGN CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide an LSI scan test design circuit capable of the scan test design of a large scale LSI in a short time and in the state of reducing fault detection omission without correcting an LSI circuit. SOLUTION: This circuit has an input terminal T for scan test mode and a latch circuit 7 for scan test design as an order circuit at ordinary time but in circuit configuration for determining the output in the manner of combination operation between the respective inputs of the latch circuit at the time of scan test. The latch circuit 7 handles the latch circuit at the time of scan test as an ordinary combination circuit, and a scan test can be applied even to a combination logic circuit up to the respective inputs of the latch circuit.