BIT SYNCHRONIZING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a bit synchronizing circuit which operates in a high-speed range of Gb/s, can make synchronization within 10 bits, can make accurate bit synchronization by suppressing jitters. SOLUTION: A multiphase clock generating circuit 2 generates a plurality of clocks which are synchronized to an input reference clock and have different phases and a phase comparator circuit 3 discriminates the phase relation between each clock and input data to be identified. Then a phase deciding circuit 5 decides the clock having the optimum phase relation, namely, level transition timing at the central part of the adjacent level transition timing of the input data. Then an identification circuit 4 and a selector 6 are provided so as to identify the input data at the level transition timing of the decided clock.