发明名称 METHOD AND CIRCUIT FOR SUPPLYING MULTI-PHASE CLOCK WITHOUT BLOCKING RELATED TO DYNAMIC LOGIC
摘要 <p>PROBLEM TO BE SOLVED: To provide a dynamic logic clock supply system with which full cycle time can be effectively utilized for logical operation without any factor to increase delay in a non-overlapped two-phase clock supply system. SOLUTION: The multi-phase clock supply system without blocking to be used for a dynamic logic applies a clock phase having an evaluation stage overlapped to a circuit provided with several cascade-connected dynamic logic gates 301-306. By appropriately allocating clock signals to the overlapped evaluation stage and the dynamic logic gates 301-306, output signals generated by the dynamic logic gates 301-306 receiving specified clock phases are utilized as input signals to the dynamic logic gates 301-306 receiving the next clock phases. Since the clock phases are overlapped, this circuit can be constituted without using any latch.</p>
申请公布号 JPH11212664(A) 申请公布日期 1999.08.06
申请号 JP19980009092 申请日期 1998.01.20
申请人 SUN MICROSYST INC 发明人 EDGARD F CLASS;DAVID W POOLE;GOULDSBERRY GARY R
分类号 G06F1/06;(IPC1-7):G06F1/06 主分类号 G06F1/06
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