发明名称 ESD PROTECTION CIRCUIT AND ITS FORMING METHOD
摘要 PROBLEM TO BE SOLVED: To simplify a process, to provide high operation voltage and to improve reliability by setting the arranging interval of dummy gate electrodes to be an interval covering the gate electrode of a second heavily doped region and metal wirings with the dummy gate electrodes and an insulated object side wall formed on the side of the electrodes. SOLUTION: Metal wirings which are electrically connected to first and second heavily doped regions 27a and 27b are formed in contact holes 30. The sizes and the intervals of dummy gate electrodes 24b are set to a degree that they cover the second heavily doped region 27b and the surface is not exposed when an insulated object side walls are formed on the side of the electrodes. The dummy gate electrodes 24b are formed on the second heavily doped region 27b with the gate electrode 24a, the side wall is formed on the side and the second heavily doped region 27b is covered with them. Thus, silicide is not formed on the area and a mask is not necessary to be uses in a silicide process even if a silicide material is loaded on the region and it is heat-treated.
申请公布号 JPH11214634(A) 申请公布日期 1999.08.06
申请号 JP19980291875 申请日期 1998.10.14
申请人 LG SEMICON CO LTD 发明人 KIM YONG-KWAN;AHN JAE GYUNG;LEE MYOUNG GOO
分类号 H01L21/28;H01L21/00;H01L21/822;H01L27/02;H01L27/04;H01L27/06;H01L29/78;(IPC1-7):H01L27/06 主分类号 H01L21/28
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