| 摘要 |
<p>PROBLEM TO BE SOLVED: To surely avoid a situation in which a reception buffer is fully occupied and runs out of time. SOLUTION: This processor has a feature in its constitution such that, during data deletion at the time of data rewrite with a flash memory 5, a parallel interface control part 2 delays a release timing of a busy signal for notifying a host device by a specified time. That is, the processor has a communication control means as its feature that, during the data deletion by a deletion means, extends a reception interval of rewrite data of a specified unit received from the host device longer than the reception interval at the time of normal mode and, after detecting completion of the data deletion by a detection means, restores the reception interval of the rewrite data of the specified unit received from the host device to the reception interval at the time of normal mode.</p> |
