发明名称 BUS INTERFACE CIRCUIT, INTEGRATED CIRCUIT AND IC CARD
摘要 PROBLEM TO BE SOLVED: To obtain a circuit to make analysis of data, etc., by a microprocessor difficult even when the data, etc., is read by providing a modulation circuit to modulate a signal in a time area and a demodulation circuit to demodulate the signal modulated in the time area. SOLUTION: An integrated circuit IC1 is provided with bus interface circuits BIF11 and BIF21 . The bus interface circuit BIF11 is provided with the modulation circuit M1. A program code, the data and a clock signal are inputted as data signals D, signal modulation is applied to these data signal D in the time axis direction, modulation data MD is generated and the modulation data MD is outputted on a bus together with a synchronizing signal SYNC for demodulation by the modulation circuit M1. The bus interface circuit BIF21 is provided with the demodulation circuit DM1. The modulation data MD modulated by the modulation circuit M1 in the bus interface circuit BIF11 . and the synchronizing signal SYNC for demodulation are received and recovered to the original program code and data by the demodulation circuit DM1. Since the signals are demodulated in this way, the analysis of the data, etc., is difficult.
申请公布号 JPH11213117(A) 申请公布日期 1999.08.06
申请号 JP19980032227 申请日期 1998.01.29
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 AOYAMA KAZUO
分类号 G06K19/07;G06K17/00;G06K19/073 主分类号 G06K19/07
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