| 摘要 |
A phase lock loop circuit includes a phase detector for receiving a reference clock and a feedback clock, a charge pump for receiving a Down pulse and an Up pulse from the phase detector, a loop filter for being charged and discharged by the output from the charge pump, and a voltage controlled oscillator for outputting a frequency signal according to the output voltage of the loop filter, the phase detector including a power cut input terminal, and when a power cut signal is input to the power cut input terminal, a Down pulse and an Up pulse output from the phase detector are forcibly changed to logic "L" level and logic "H" level, respectively, which reduces the power consumption in the phase locked loop circuit.
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