发明名称 Computer system and inter-bus control circuit
摘要 In a computer system having a double PCI bus configuration, an inter-bus control circuit for relaying a first PCI bus and a second PCI bus is provided with a memory control mechanism common to devices connected to the second PCI bus and an interrupt control mechanism for controlling interrupts between local processors, in addition to a control function for controlling the buses. The inter-bus control circuit having the above mechanisms can be implemented by a single-chip integrated circuit. The integrated inter-bus control circuit prevents the use of a plurality of identical decoder circuits, an increase in the number of parts, and an increase in mounting area, thus providing a compact and low price computer system.
申请公布号 US5933613(A) 申请公布日期 1999.08.03
申请号 US19960675118 申请日期 1996.07.03
申请人 HITACHI, LTD. 发明人 TANAKA, TOSHIO;ISHIDA, KAZUHISA;KIYOMATSU, TETSURO;TSUJIOKA, SHIGEO
分类号 G06F13/40;(IPC1-7):G06F13/24 主分类号 G06F13/40
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