Divided word line architecture for embedded memories using multiple metal layers

摘要

A semiconductor memory architecture is disclosed which results in reduced power dissipation. This reduction is accomplished by partitioning the word line of an array into segments thereby forming selectable blocks within the array. The power is reduced by the number of blocks by which the array can be partitioned. The word line segments are routed to a central decoder with a block select provision. Routing is accomplished with interconnect lines which are typically metal layers. The array remains continuous in spite of block partitioning.