| 摘要 |
PURPOSE:To provide element isolation with a small size by isolating a first active region interposed between the two grooves of a substrate and a second active region in the groove bottom, and forming a memory transistor in the active regions. CONSTITUTION:Silicon in a p-well 1 is removed to form a groove 8, thereby defining a first active region with the groove 8 and a field oxide film 2. Then, an insulating film 9a for element isolation is formed in the side wall of the groove 8. The portion of the bottom surface of the groove which is not covered with the insulating film 9a becomes a second active region. Then, after depositing a tungsten silicide film 13 over the whole surface, branch lines 13 (X1) to 13 (X16) of a word line, which also acts as a gate electrode, and unit select lines US1 and US2 are formed. Thereafter, an insulating spacer is formed in the side wall of the branch line 13 (X1) and the like of the word line. Then, phosphorous ions are implanted into the first and second active regions to form a code implation layer, thereby making the selection transistor a depletion type. Since the width of the side wall insulating film is not restricted by lithography, the chip size can be made small. |
