发明名称 Timing interpolator in digital demodulator
摘要 A timing interpolator for re-controlling a symbol timing in a digital demodulator for converting a received analog signal to a digital signal is disclosed. The timing interpolator comprises an address generator for inputting M number of fractional intervals between 0 to 1 at each clock, and generating addresses from the fractional intervals; a memory for storing sine function values corresponding to the M number of fractional intervals, and outputting sine function values corresponding to the addresses from the address generator; a tap-coefficient calculator for receiving the filter index, the fractional intervals, and the sine function values, to calculate a tap-coefficient; and a digital filter having L+1 number of taps to filter an input signal by using the calculated tap-coefficient obtained from the tap-coefficient generator, and outputting the filtered signal. By using this structure, the timing interpolator stores M number of sine function values in the memory according to the variation of the filter index, the fractional interval, and the fractional interval instead of (L+1)xM number of tap-coefficients, such that the interpolator's memory decreases by as much as 1/(L+1) by using the stored sine function values to directly calculate the tap-coefficients.
申请公布号 US5933452(A) 申请公布日期 1999.08.03
申请号 US19970916203 申请日期 1997.08.22
申请人 DAEWOO ELECTRONICS CO., LTD. 发明人 EUN, MYUNG-SU
分类号 H03H17/00;H03H17/06;H04L7/00;H04L7/02;H04L25/17;H04L27/22;H04L27/38;(IPC1-7):H03H7/30 主分类号 H03H17/00
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