发明名称 |
Logic circuit design apparatus |
摘要 |
A logic circuit design apparatus capable of designing scan circuits for uses peculiar to the logic circuit and scan circuits for test pattern generation simplification with ease is disclosed. The logic circuit design apparatus comprises a storage part, an acquisition part, a user resister design part, and a data chain design part. The storage part stores a circuit data of a logic circuit whose logic design for normal operation. The acquisition part acquires a design data which specifies a user resister that is a scan circuit to be designed on the logical circuit whose circuit data is stored in the storage part. The user resister design part designs a user resister corresponding the design data acquired by the acquisition part. The data chain design part designs a data chain which is a scan circuit for test pattern generation simplification by utilizing the user register designed by the user register design part.
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申请公布号 |
US5933619(A) |
申请公布日期 |
1999.08.03 |
申请号 |
US19960604617 |
申请日期 |
1996.02.21 |
申请人 |
FUJITSU LIMITED |
发明人 |
FURUTA, EIJI;FUKASE, HISATAKA |
分类号 |
G06F17/50;G01R31/3185;(IPC1-7):G06F17/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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