发明名称 METHOD AND APPARATUS FOR SOURCE SYNCHRONOUS DATA TRANSFER
摘要 A method and apparatus is presented for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e.g., on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines (14) and data signals can be sent on a data signal line (13), the component (12) receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.
申请公布号 WO9938295(A1) 申请公布日期 1999.07.29
申请号 WO1999US01747 申请日期 1999.01.26
申请人 INTEL CORPORATION 发明人 KELLY, TIMOTHY, W.;PAWLOWSKI, STEPHEN, S.;SELF, KEITH, M.;SMITH, JEFFREY, E.
分类号 H04L7/00;H04L7/033;(IPC1-7):H04L23/00;H04B1/38;H04L5/16 主分类号 H04L7/00
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