Multiport analyzing time stamp synchronizing and parallel communicating

摘要

A plurality of digital transmission network analyzers (36) are arranged to analyze and compare the appearance of a data packet on the plurality of ports of a network (12). Each analyzer (36) has its own internal clock (50) for time stamping of data packets in addition to other internal timing purposes. In order to synchronize the time stamping of the packet as it appears to each analyzer at each different port, the clock outputs of the several analyzers are connected together; and a controlling CPU (40) commands one of the analyzers to supply the master clock to the others. That master analyzer then commands the other analyzers to disable or disconnect their own clocks, thereby all of the analyzers involved in a given test are under timing control of the clock of the master analyzer. Packet headers and time stamps are transmitted between analyzers for comparison, analysis and reporting to the controlling CPU. This analyzer intercommunication is effected over a separate bus (42) that interconnects all of the analyzers and the controlling CPU.