发明名称 Apparatus and method for calculating Bc (mod n)
摘要 Apparatus method for calculating the remainder of BC modulo n at high speed with minimum hardware resources, while securing the safety of the key in a cryptographic system. The apparatus comprises circuitry including registers for executing an initial and normal cycles, cumulating and storing the calculation result of each cycle and for outputting from a least significant bit. The initial cycle of the calculation includes a step of calculating a remainder of an m-bit input modulo n and a step of holding the result of the calculation. The normal cycle of the calculation includes a step of doubling the result of the calculation, and calculating a remainder of the doubled result of the calculation modulo n and a step of holding the next result of the calculation and for repeatedly executing the normal cycle m-2 times after the first normal cycle. The calculation result of each previous normal cycle is used in each successive normal cycle.
申请公布号 US5928315(A) 申请公布日期 1999.07.27
申请号 US19970928538 申请日期 1997.09.12
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 KOBAYASHI, YOSHINAO;SATOH, AKASHI;NIIJIMA, HIDETO
分类号 G06F7/72;(IPC1-7):G06F7/72 主分类号 G06F7/72
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