| 摘要 |
A microprocessor configured to detect a plurality of consecutive instructions comprising a predefined instruction sequence is provided. The predefined sequence indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, the number of subsequent instructions which belong to the alternate instruction set is encoded in the predefined instruction sequence. The subsequent instructions are routed to an execution unit or a separate processor for execution. Each instruction sequence within a program may be coded using the instruction set which most efficiently executes the function corresponding to the instruction sequence. In one embodiment, the microprocessor executes the x86 instruction set and the alternate instruction set is the ADSP 2171 instruction set. The predefined instruction sequence may comprise MOV instructions having the same destination, or identical XOR instructions. Portions of the program which may be executed more efficiently using x86 instructions may be coded in the x86 instruction set, while portions of the program which may be executed more efficiently using DSP instructions may be coded in the DSP instruction set. Each of the above portions is separated from other portions by the predefined instruction sequence, so that the microprocessor may determine which instruction set the instructions belong to.
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