| 摘要 |
A divide-by-4/5 counter includes a half transparent register, a domino logic, a buffer, a divide-by-4 counter and a control circuit. The half transparent register includes first, second, and third NMOS and PMOS transistors and first and second inverters. The domino logic includes fourth PMOS and NMOS transistors and first and second switches. The buffer is connected to a drain of the fourth PMOS transistor for out putting a reference clock signal. The divide-by-4 counter includes two divide-by-2 counters to obtain a divide-by-2 clock signal and an output clock signal. The control circuit is connected to a control terminal of the second switch for outputting a control signal of the domino logic according to the divide-by-2 clock signal, the output clock signal and a divide-by-4/5 control signal.
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