| 摘要 |
A Blt accelerator method and apparatus (10) are disclosed. A sequencing engine (18) generates appropriate source and destination addresses in response to values stored in host addressable registers (16). Data are read into a storage unit (22) in an initial Blt operation. In subsequent Blt operations data are read from a source data location in combination with the data from the storage unit (22) into an arithmetic logic unit (ALU) (20). The ALU (20) performs a selected arithmetic/logic operation on the input data and stores the result back in the storage unit (22). In this manner, consecutive, subsequent, chained Blt operations may accumulate data. Shift circuits (34) and saturation add capabilities of the ALU (20) are further provided along with methods for the acceleration of pixel filtering, interpolation, and blending, as well as motion compensation in MPEG decoding.
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