发明名称 |
One-chip LSI including a general memory and a logic |
摘要 |
An LSI chip has a main surface occupied by a logic section, a data input/output section and a memory macro section. The memory macro section is a rectangular section arranged on the main surface of the LSI chip. A test control circuit is arranged along one side of the memory macro section. A data input/output circuit is arranged along another side of the memory macro section. The test control circuit may be arranged along one side of the LSI chip. Test data is supplied from the test control circuit to the data input/output circuit through a data bus. As a result, a load of designing a memory logic LSI can be lightened.
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申请公布号 |
US5930187(A) |
申请公布日期 |
1999.07.27 |
申请号 |
US19970962358 |
申请日期 |
1997.10.31 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SATO, KATSUHIKO;MIYANO, SHINJI |
分类号 |
G06F15/78;G01R31/3185;G11C5/02;G11C11/401;G11C29/12;H01L21/822;H01L27/04;H01L27/10;(IPC1-7):G11C7/00 |
主分类号 |
G06F15/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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