发明名称 Clamping divider, processor having clamping divider, and method for clamping in division
摘要 A clamping divider has a bit shifter, a multiple accumulator (MAC), and an output circuit. When executing a division with the use of a clamp value of 2m, the bit shifter shifts one of the divisor and dividend of the division, and the MAC subtracts the shifted one from the other to determine, before calculating a quotient of the division, whether or not a result of the division must be clamped.
申请公布号 US5928318(A) 申请公布日期 1999.07.27
申请号 US19970923926 申请日期 1997.09.05
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 ARAKI, YOSHITSUGU
分类号 G06F7/38;G06F7/52;G06F7/535;(IPC1-7):G06F7/52 主分类号 G06F7/38
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