| 发明名称 |
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| 摘要 |
A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers (60) to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip (52). Opposite rows of substantially flat cantilevered lead-fingers (60) are attached by double-sided adhesive tape (55) in thermal contact with the active face of a chip (52). The lead-fingers (60) are routed in personalized paths over the face of the chip (52) to cover a large surface area to aid heat dissipation. All wirebond connections (63) between the lead-fingers (60) and the chip (52) are made at a centerline connection strip running down the center of the chip (52). Each of the cantilevered lead-fingers (60) has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face. |
| 申请公布号 |
JP2923236(B2) |
申请公布日期 |
1999.07.26 |
| 申请号 |
JP19950279103 |
申请日期 |
1995.10.26 |
| 申请人 |
INTAANASHONARU BIJINESU MASHIINZU CORP;JIIMENSU AG |
发明人 |
HARORUDO UOODO KONRUU;FURANSHISU YUUJINNU FUROOBERU;ARUBAATO JON GUREGORITSUCHI JUNIA;SHERUDON KOORU RIIRII;SUTEFUAN JOOJI SUTAA;RONARUDO ROBAATO ATSUTOREHITO;ERITSUKU JEFURII HOWAITO;JENSU GYUNTERU H |
| 分类号 |
H01L23/50;H01L23/00;H01L23/495 |
主分类号 |
H01L23/50 |
| 代理机构 |
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