| 摘要 |
PURPOSE:To provide a clock generating circuit which can operate at a high speed and at a low level of voltage. CONSTITUTION:A shift register, e.g. a 4-bit unidirectional shift register connected vertically transmits the signals QA, QB, QC and QD. These signals are selected by a shifting direction switch signal SHL and a controllable clocked NAND gate. So that the output shifting directions of divided clocks PHI1-PHI14 can be switched from a basic clock XCK. |
