Memory cell arrangement with several threshold levels

摘要

The circuit has a current comparator arrangement (10) which compares a current flowing on a bit conductor and a reference current (Iref). A memory arrangement stores the result of the comparison, and a counter register arrangement is provided in such way that it corresponds to an amount of several threshold levels of the memory cell. The circuit has a switch arrangement (NM33) for applying or blocking a current (Izelle) to or from a memory cell in response to a switch control signal which is entered in a bit conductor connected with a selected memory cell. A current comparator arrangement (10) compares a current flowing on the bit conductor and a reference current (Iref), and outputs a result (SAUS). A memory arrangement stores the result of the comparison, and a counter register arrangement is provided in such way that it corresponds to an amount of several threshold levels of the memory cell.