ADDRESS DECODING DEVICE FOR SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To improve a dead-access time by shortening the time needed to secure operation up to the enabling of a decoder after an address is applied. SOLUTION: This address decoding device includes an address latch 32 which receives address signals Ai and Aj and generates an effective address RAij in response an internal clock PCLK and an active instruction PRA, a predecoder 34 which predecodes the effective address RAij from the address latch 32 and outputs the predecoded address DRAij, and a main decoder 36 which receives the predecoded address DRAij assigned by banks, performs main decoding and sufficiently boosts the voltage, and drives a word line with the boosted voltage. The predecoder 34 is enabled before an effective row address is generated by the address latch. The predecoder 34 is disabled right after the decoded address DRAij is generated and the effective row address DRAij is reset after the predecoder 34 is disabled.