| 摘要 |
<p>In accordance with the present invention, a flash memory region of a memory device (20) includes a silicon substrate (22), a plurality of memory stacks (26) formed on the silicon substrate (22). A moat (42) is formed between at least two of the plurality of memory stacks (26), with the silicon substrate (22) being exposed in the moat (22). A sidewall spacer (40) formed on each of the opposing sidewalls of each of the stacks adjacent the moat. Each of the stack (26) is encapsulated by dielectric (48). A dielectric layer (48) overlies the encapsulated stacks (26), and forms a slot-shaped contact aperture (14) therein exposing the silicon substrate in each of the moats (42). The aperture (14) has an elongated shape and extends transversely with the moat. A metal line (52) is positioned in the contact aperture to extend over the stacks and into the moat, and is in electrical contact with the silicon substrate (20) to form a continuous electrically conduction runner. A delectric layer (54) overlies the metal line to encapsulate the metal line (52). <IMAGE> <IMAGE></p> |
