| 摘要 |
<p>A parallel processor (21) capable of exhibiting a high processing performance, which when receiving as input access requests generating page faults to sub-banks (271, 272, 273) from a plurality of processor elements (231, 232, ...23n) connected to a common bus (22) and another access request is input while data is being transferred between sub-banks (271, 272, 273) and an external memory (7) via an external access bus (26) in response to the input access requests, a shared memory (24) stores the other access request in a request queue and makes a control circuit execute the stored access request when the stored access request does not generate a page fault. <IMAGE></p> |
