| 摘要 |
A buffer circuit which can solve a problem of a conventional buffer circuit in that high speed data transfer is hindered because of parasitic capacitance of signal lines, which has an affect on the discharge time of inverters in a latch circuit of the buffer circuit, when the buffer circuit changes its state from a first term (non-transfer mode) to a second term (transfer mode). The buffer circuit solves this problem by pouring a current, which flows thereinto from a first signal line, into ground through a first PMOS transistor, a first NMOS transistor and a third NMOS transistor, and by pouring a current, which flows thereinto from a second signal line, into the ground through a second PMOS transistor, a second NMOS transistor and the third NMOS transistor.
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