发明名称 |
Semiconductor memory device with data scramble circuit |
摘要 |
The semiconductor memory device of the present invention comprises a mode setting means for setting the test mode; a circuit for transferring data provided to one of the input/output pins in a group of a given number of input/output pins to each of the rest of the group when the test mode is set; a circuit provided for each input/output pin which, when the test mode is set, selectively inverting the data signal values provided to the input/output pins or retrieved from the memory cells so that the order of the specified logical addresses coincides with the order of the physical addresses of the memory cells; and a circuit for deciding whether or not the data reading operation has been properly performed from the data retrieved from the memory cells to the given number of input/output pins and for sending out a signal indicating the decision to one of the input/output pins in the group of the given number of input/output pins. |
申请公布号 |
US5925141(A) |
申请公布日期 |
1999.07.20 |
申请号 |
US19970904593 |
申请日期 |
1997.08.01 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ARIKI, TAKUYA |
分类号 |
G01R31/28;G01R31/3185;G11C29/12;G11C29/34;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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