| 摘要 |
This invention relates to the structure of multiple registers used in image signal processing, and aims to simplify the register structure and to reduce the power consumption of the registers and the time required for testing an image signal processing LSI with the registers. A semiconductor integrated circuit according to the invention has a clock generation circuit and a clock buffer circuit for generating a plurality of clock signals, a register group including a plurality of registers connected in series and operable in synchronism with the clock signals, at least one combinational circuit connected to the register group, and means for selecting one of a normal operation mode and a scan test mode for the register group. The clock generation circuit receives a system clock CPIN, a scan test mode selection signal SMODEN, and clock CPSIN, and outputs a clock phi and a clock ( phi 1 bar) controlled by the signal SMODEN such that the clocks have periods of "1" kept from overlapping each other, and also outputs a writing clock CPS used in the scan test mode. Since the register group is operated using the clocks, it is not necessary to form all registers of scan registers. As a result, the register group can be formed in a small area and made scannable. Moreover, the chip size and the power consumption can be further reduced by locating the clock buffer circuit adjacent to the register group.
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