Geometrical layout technique for a circular capacitor within an array of matched capacitors on a semiconductor device

摘要

A geometrical layout technique for an individual circular capacitor in a semiconductor device. Circular capacitors reduce the detrimental effects of (1) corner etching, (2) peripheral capacitance, (3) capacitor to capacitor coupling, and (4) electric field anomalies and result in superior capacitor matching. The circular capacitor is comprised of a circular bottom plate made of a conducting material, a circular dielectric material coupled to the bottom plate and a circular top plate made of a conducting material. The circular capacitors may be arranged as an array in either a rectangular lattice layout or a diagonal lattice layout. These lattice layouts take advantage of the elimination or reduction of the problems encountered in the prior art such as corner etching, peripheral capacitance, capacitor to capacitor coupling and electric field anomalies.