| 摘要 |
A data processing system and method for maintaining coherency between a high-level (L2) cache and a low-level (L1) cache are disclosed. The L2 (high-level) cache operates in a first mode of operation where a cache line is in a modified and inclusive state, and in a second mode of operation where a cache line is in an invalid and inclusive state. Initially, the high-level cache snoops a request from another computing unit for access to data previously stored in the high-level cache. Next, the high-level cache communicates to the computing unit not to access the area of memory containing the data for some time. The high-level cache then determines if the requested data stored in the high-level cache is invalid or modified, and possibly stored in the low-level cache. The high-level cache then queries the low-level cache to determine if the data is in the low-level cache. If the data is contained in the low-level cache and is modified, the data is returned from the low-level cache to the high-level cache, and from there is written to memory. In the first mode of operation, if no data is returned, and the data in the high-level cache is marked as modified, the data in the high-level cache is written to memory. In the second mode of operation, if no data is returned, the high-level cache does not write any data to memory. In another embodiment, the high-level cache utilizes the state of a line's low-level Inclusive bit when the cache line's MESI (modified, exclusive, shared, invalid) bits are set to the Invalid state. Initially, data is stored in the low.level cache and the high-level cache. Next, the processor modifies the data and stores the modified data in the low-level cache. The high-level cache may also resolve collisions between a processor request and a system request originating form another computing unit and avoid sending a RETRY signal to the processor. An efficient pipelined algorithm for flushing the high level (L2) cache and back invalidating the low-level (L1) cache is also described. The data in the high-level cache is then marked as possibly available in the low-level cache and invalid in the high-level cache. This allows for coherency to be maintained between the high-level and low-level caches without transferring data from the low-level cache to the high-level cache.
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