| 摘要 |
A bipolar four-quadrant analog multiplier that is formed on a semiconductor integrated circuit device and is capable of low-voltage operation at a voltage as low as 1 V while the input voltage range providing a good linearity is enlarged. This multiplier contains a multitail cell made of a first transistor pair of first and second bipolar transistors, a second transistor pair of third and fourth bipolar transistors, and at least one bipolar transistor. The first and second transistors have output ends coupled together to form one of differential output ends of the multiplier. The third and fourth transistors have output ends coupled together to form the other of the differential output ends. The first to fifth transistors are driven by a common tail current. The first, second, third, fourth and fifth transistors are applied with (aVx+bVy), ((a-1)Vx+(b-1)Vy), ((a-1)Vx+bVy), (aVx+(b-1)Vy), and ({a-(+E,fra 1/2+EE }Vx+{b-(+E,fra 1/2+EE )}Vy+Vc), respectively, where Vx and Vy are initial input signals to be multiplied, a and b are constants, and Vc is a positive dc voltage.
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