发明名称 |
Active load for an N channel logic network |
摘要 |
An active load (12) is provided for an N channel logic network (10). The active load (12) includes a P channel device (28) coupled to the output node (14) of the N channel network (10). A clock circuit (16) of the active load (12) determines whether the N channel network (10) is in a steady state or a switching mode. If the N channel network (10) is in a switching mode, an intermediate voltage level, Vbias, is applied at the gate of the P channel device (28) to facilitate fast switching at the output node (14) with low quiescent power consumption and without compromising compact semiconductor layout.
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申请公布号 |
US5926039(A) |
申请公布日期 |
1999.07.20 |
申请号 |
US19970820728 |
申请日期 |
1997.03.19 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MAHANT-SHETTI, SHIVALING S.;RAO, KAMESHWAR C. |
分类号 |
H03K19/017;H03K19/096;(IPC1-7):H03K19/096 |
主分类号 |
H03K19/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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