| 摘要 |
A voltage doubling circuit provides an output voltage, for supply to a capacitive load, which is nearly double the positive supply voltage. During one phase of a clock signal, a capacitor is charged so that the positive supply voltage appears on one terminal and the negative supply voltage appears on the other terminal thereof while, during the other phase of the clock signal, the terminal formerly held at the negative supply voltage is clamped to the positive supply voltage, and the output increases to nearly double the positive supply. |
